发明名称 MEMORY-TESTING DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To reduce test time and time required for rescue judgment processing by storing a bad block data for indicating a faulty block at a block address that is composed of bits for selecting an address signal being fed to a memory to be tested each time when the faulty block is detected. SOLUTION: When data, which is read from a memory MUT to be tested, mismatch with an expectation value from a pattern generator PG, a mismatched address and the position of a memory cell are stored at a fault analysis memory AFM, and data for indicating a back block is written to a block address corresponding to a block where the mismatched address belongs is written to a first back block memory BBM. When there are a plurality of memories MUT, the test of the memories MUT where a bad block is accessed is masked by the bad data, and the testing of the block can be immediately executed for the memories MUT where other write has been completed.</p>
申请公布号 JP2000100196(A) 申请公布日期 2000.04.07
申请号 JP19980266332 申请日期 1998.09.21
申请人 ADVANTEST CORP 发明人 SATO KAZUHIKO
分类号 G11C16/06;G01R31/28;G11C29/00;G11C29/44;G11C29/56;(IPC1-7):G11C29/00 主分类号 G11C16/06
代理机构 代理人
主权项
地址