Process and circuit arrangement for generating a clock signal

摘要

The clock signal is input (CKIN) and passed through a phase comparison circuit (MCD) and compared with a synchronized synthesized output (SYF). The output from the comparator is passed back to the synchronized synthesizer, using one of two logic states (SC1). Dependent on whether the clock signal is behind or advanced, the logic passes the synthesized signal or clock signal. An Independent claim is included for a clock generation device.