发明名称 Electro-static discharge protection of CMOS integrated circuits
摘要 In a semiconductor integrated circuit, I/O buffer circuits that include ESD protection are generally provided for each I/O pad. According to the invention, unused pads, i.e. pads that are not connected to core circuitry according to an initial design, are connected to other pads that are used for connection to the core circuitry, thereby employing the unused pads to improve ESD protection of susceptible pads. This approach has the advantages of greater ESD protection without increasing silicon area and without adding any additional steps to the usual fabrication process. The inventive concept is especially useful for augmenting ESD protection of corner pads without requiring new or custom ESD protection circuits. This invention can be easily implemented into known layout tools.
申请公布号 US6043539(A) 申请公布日期 2000.03.28
申请号 US19970978979 申请日期 1997.11.26
申请人 LSI LOGIC CORPORATION 发明人 SUGASAWARA, EMERY
分类号 H01L23/60;H01L23/62;(IPC1-7):H01L23/60 主分类号 H01L23/60
代理机构 代理人
主权项
地址