| 摘要 |
A phase lock loop (PLL) provides a method and apparatus for recovering a clock signal from input digital signal, such as serial data, in the presence of both jitter and stressful or pathological input bit patterns having low data transition density. The PLL comprises a bang-bang phase detector comprising a phase comparator and a bi-stable charge pump and a voltage controlled oscillator (VCO). Irrespective of the magnitude of the error or difference between the phase of an incoming digital signal and the recovered clock signal, the rate of change in the phase of the recovered clock signal (12) is fixed and ramps either upwardly or downwardly. The alignment jitter of the PLL is limited for any input jitter such that the maximum allowable alignment jitter limit for any digital communication standard can be met. The slew PLL circuit also does not suffer from the undesirable momentary phase shifts caused by noise which is injected into the VCO when the input digital signal has low data transition density. The slew PLL may also be used in a serializer. |
