| 摘要 |
PURPOSE: A memory device capable of a high speed random access is provided, which can exchange a column access mode and a random access mode. CONSTITUTION: The memory device capable of a high speed random access comprises: a first stage (100) for performing a command decode; a second stage (200) for performing an activating of a sense amplifier (SA); and a third stage (300) for performing an input/output of data. The second stage (200) responds to a first reading or writing command and transmits data between the sense amplifier (SA) and the third stage (300), and then inactivates the sense amplifier (SA). The second stage (200) responds a second reading or writing command and transmits data between the sense amplifier (SA) and the third stage (300), and then activates the sense amplifier (SA) and does not perform a reset operation. Thereby, it is possible to perform a high speed reading and writing operation.
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