| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to realize phase synchronization even when a load is changed in a timing control circuit using a synchronous mirror delay circuit. SOLUTION: A reference clock signal clkin11 is inputted to a timing control circuit SMDF11, which generates an internal clock dclk11 by using the signal clkin11 and an external clock clkout11 generated through a buffer circuit BUF11. The external clock signal clkout11 is fed back and inputted to the circuit SMDF11, which generates the internal clock signal dclk11 so that the phase of the signal clkout11 is the same as that of the reference clock signal clkin11. The circuit SMDF11 has a circuit (FDA11, MCC11) for detecting a phase difference between the internal clock and the external clock and a delay circuit DCL11 capable of controlling delay quantity and the delay circuit can change the delay quantity by the detected phase difference. |
