| 摘要 |
PCT No. PCT/JP92/01078 Sec. 371 Date Apr. 13, 1993 Sec. 102(e) Date Apr. 13, 1993 PCT Filed Aug. 26, 1992 PCT Pub. No. WO93/04476 PCT Pub. Date Mar. 4, 1993.A noise resistant static memory device is presented which is capable of reading correct data from the memory cells even in the presence of a sharp pulse noise. This is achieved by providing a signal change detection circuit which detects that a extraneous signal having a very short pulse width has been included in the read out data. In the conventional design based on auto power-down system, this type of sharp pulse will result in the destruction of the latched data because of automatic resetting of the memory read out circuit. In the invented device, resetting is nullified simultaneously with the detection of the noise signal, thereby enabling the data read out circuit to read the data again, thereby enabling to repeat the reading step. The device thus provides noise-resistant reliable memory read out performance. |
