发明名称 |
Universal DRAM address multiplexer |
摘要 |
This invention relates to a method and circuit for addressing a symmetric or asymmetric 2M-element DRAM module using identical circuitry. The method consists of receiving an original address comprising M bits 0 to M-1 identifying a specific memory element, then deriving from these bits a column address and a row address which together identify the specific memory element. The column address comprises N bits 0 to N-1 which match in direct order bits 0 to N-1 of the original address and the row address comprises N bits 0 to N-1 which match in reverse order bits N-2 to M-1 of the original address. A circuit for selectively connecting a set of input address lines to a set of output address lines in a column mapping or a row mapping is also disclosed. The circuit comprises M input address lines 0 to M-1 and N output address lines 0 to N-1. The column mapping associates output address lines 0 to N-1 with input address lines 0 to N-1 in direct order, and the row mapping associates output address lines 0 to N-1 with input address lines N-2 to M-1 in reverse order. The circuit may also comprise a strobe signal for selecting between the column mapping and the row mapping.
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申请公布号 |
US6038637(A) |
申请公布日期 |
2000.03.14 |
申请号 |
US19970978476 |
申请日期 |
1997.11.25 |
申请人 |
NORTEL NETWORKS CORPORATION |
发明人 |
BERUBE, JEAN LUC JOSEPH;PARFITT, STEWART JOHN;YOUNG, DEAN JAMES;KNIGHT, DOUG N. |
分类号 |
G11C8/00;G11C11/408;(IPC1-7):G06F12/00 |
主分类号 |
G11C8/00 |
代理机构 |
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地址 |
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