发明名称 |
Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes |
摘要 |
A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate structure, polysilicon hard masks and polysilicon spacers are used as etching masks in a self-aligned contact process. In addition, the landing plugs incorporate the polysilicon spacers as part of landing plug to increase the contact area. As a result, wide contact processing windows can be achieved in high density integrated circuits.
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申请公布号 |
US6037211(A) |
申请公布日期 |
2000.03.14 |
申请号 |
US19970841836 |
申请日期 |
1997.05.05 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
JENG, ERIK S.;CHEN, YUE-FENG;CHEN, BI-LING |
分类号 |
H01L21/60;H01L21/768;H01L21/8242;(IPC1-7):H01L21/28;H01L21/336;H01L21/824 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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