| 摘要 |
PROBLEM TO BE SOLVED: To supply a clock for a period between a reset signal is inputted and PLL is completed by selecting the inputted clock for a period till the phase of a PLL circuit is locked after a reset signal is inputted and selecting the clock outputted from the PLL circuit after the phase of the PLL circuit is locked. SOLUTION: An inputted original clock 14 is fed back to a PLL 11 via a clock driver 12 and a loop buffer 17. The PLL 11 automatically controls and outputs an output clock so as to secure synchronization between the inputted original clock 14 and a fed-back clock. A clock control means 16 controls every selector 15 to output the clock 14 before the clock synchronization is secured and then to output the clock that is outputted from the PLL 11 after the synchronization of the PLL 11 is secured. Since other peripheral circuits can be initialized by outputting the clock 14, the start-up time is shortened for a clock control circuit. |
