| 摘要 |
PROBLEM TO BE SOLVED: To enable forming a gate pattern of a cell transistor and a gate pattern of an MOS transistor of a peripheral circuit in the same process step, and bring a gate electrode of the MOS transistor and a resistor which are formed in the peripheral circuit directly into contact with metal wiring. SOLUTION: A second conducting pattern formed in a cell array region and an MOS transistor region, a dielectric film 11 and a first conducting pattern are continuously patterned, and a gate pattern of a cell transistor and a gate pattern of an MOS transistor are simultaneously formed. The gate pattern of the MOS transistor contains a specified region of the dielectric film 11 exposed when the second conducting pattern is formed. An interlayer insulating film 17 is formed on the whole surface of a result object on which the gate pattern is formed, and contact holes exposing a gate electrode 9g of the MOS transistor and a specified region of a resistor pattern 9r are formed by patterning the interlayer insulating film 17. |
