发明名称 TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce noise generated by the variation of power source current and signal current in the case where logical state of each device simultaneously varys in a simultaneous testing of plural devices. SOLUTION: A plurality of devices to be measured 18a, 18b, 18c and 18d are simultaneously tested. In this case, by shifting input timings of test signals for each semiconductor integrated circuit to be measured, the timing of generating noise on the power source line and ground line are shifted.
申请公布号 JP2000074983(A) 申请公布日期 2000.03.14
申请号 JP19980240969 申请日期 1998.08.27
申请人 SHARP CORP 发明人 TOYODA HIROYUKI
分类号 G01R31/26;(IPC1-7):G01R31/26 主分类号 G01R31/26
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