发明名称 |
Computer system with power management scheme for DRAM devices |
摘要 |
A computer system employs DRAM devices in a memory sub-system, which devices are assigned into particular pools corresponding to different power consumption states with a most-recently-accessed (MRA) device being assigned to an active pool and placed at the top of a stack structure. A LRA device in the active pool is evicted from the active pool and placed in a standby pool when the active pool is full and the processor accesses another device, which is not currently assigned to the active pool. A LRA device of the standby pool gets evicted into a nap pool upon one of two conditions: either a timeout occurs, or the standby and active pools are full and the processor accesses another device, which is not currently assigned to either the active or standby pools.
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申请公布号 |
US6038673(A) |
申请公布日期 |
2000.03.14 |
申请号 |
US19980186290 |
申请日期 |
1998.11.03 |
申请人 |
INTEL CORPORATION |
发明人 |
BENN, SAMUEL D.;WILLIAMS, MICHAEL W. |
分类号 |
G06F1/32;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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