发明名称 Modified test module for integrated circuit is used to resynchronize circuit with clock and containing several independently developed modules
摘要 The test module (840) contains four multiplexers (843-846) and two flip-flops (841,842) and receives an input from a synchronous circuit (830) producing a clock signal (H1). This circuit has connections to the first and fourth multiplexers. The fourth multiplexer receives input signals (DI) from other modules.
申请公布号 FR2783111(A1) 申请公布日期 2000.03.10
申请号 FR19980011384 申请日期 1998.09.08
申请人 STMICROELECTRONICS SA 发明人 FORGET NOEL
分类号 G01R31/3185;(IPC1-7):H03K5/01;G06F1/12 主分类号 G01R31/3185
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