| 摘要 |
BHRAM is a system of organizing Dynamic RAM memory for increased burst speeds by means of INFRACYCLE MULTIPLEXING. Any technology of high speed DRAM may be employed, such as EDO RAM, or SDRAM, but synchronous DRAM is the preferred technology due to speed and timing regularity. Addressing of the DRAM and data READ and WRITE follows the conventional RAS and CAS cycles for that technology, including the banking structure for burst mode operation, but with an important variation, detailed in the SPECIFICATION. What is added by BHRAM is the ability to read and write data multiple times during a single burst clock cycle, using infracycle multiplexing. Thus, if the SDRAM provides a burst speed of 100 Mhz. on a 100 Mhz. memory bus, then effectively BHRAM can provide a speed of, nominally, 400 Mhz, data access on the same bus. This can be extended to include DRAM on a chip with SRAM to provide very fast cacheing.
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