TRUE/COMPLEMENT REDUNDANCY SCHEME IN A SEMICONDUCTOR MEMORY DEVIDE

摘要

PURPOSE: A true/complement redundancy scheme is provided to improve an operation speed of redundancy. CONSTITUTION: The true/complement redundancy scheme comprises: a plurality of memory blocks sharing main word lines, the respective block further comprising a plurality of sub word lines, a plurality of bit lines transposed with the sub word lines and a plurality of memory cells in the transposed position of the sub word lines and the bit lines; a plurality of block sense amplifier circuits connected to the cell blocks; a redundant memory block having a plurality of redundant bit lines to which a plurality of redundant memory cells are connected, disposed in the same region as one of the memory blocks; a redundancy controller for generating a sense amplifier control signal, a first selection signal and a second selection signal in response to column address signals when a memory cell addressed by row and column address signals supplied through an address buffer circuit from the exterior is a defect cell; and a redundant decoder circuit for selecting at least one of the redundant columns in response to the second selection signals.