发明名称 SYNCHRONOUS SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To flexibly adjust operating margins of chips with respect to an external clock signal by performing the fetching operation of write data and the outputting operation of read out data in synchronization with a first internal clock signal which has the N-fold frequency of that of the external clock signal while being synchronized with the inputting external signal or a second internal clock signal which is synchronized with the external clock signal. SOLUTION: In a second operating mode, a data input-output circuit 1086 converts N pieces of data in parallel which are supplied serially in synchronization with the first internal clock signal to supply write data to selected N pieces of memeory cells. At the of reading data, the circuit receives readout data from selected N pieces of memeory cells in parallel to convert them into N pieces of serial data and it performs the outputting operation of the read out data in synchronization with the first internal clock signal, In a first operating mode, the fetching operation of write data and the outputting operation of read out data are performed in synchronization with the second internal clock signal.</p>
申请公布号 JP2000067577(A) 申请公布日期 2000.03.03
申请号 JP19980292561 申请日期 1998.10.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 OISHI TSUKASA;ISHIKAWA MASATOSHI
分类号 G11C11/413;G11C7/10;G11C11/407;(IPC1-7):G11C11/407 主分类号 G11C11/413
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