发明名称 Method of forming a multi-level interconnection in a ferroelectric memory device
摘要 A method for fabricating a ferroelectric memory device comprising forming contact plugs 14a-e in a first insulating layer 12 upon a substrate 10 having transistors formed therein; forming a first conductive layer 16, a ferroelectric film 17 and a second conductive layer 18; etching layers 16, 17 and 18 to form capacitor patterns 20, 21, 22, 23 and first conductive layer patterns 16b, 16c, 16e, 16g; forming a second insulating layer 30, etching first contact holes to the first conductive layer patterns and then depositing a first conductive material to form a first level interconnection 32a-d; forming a third insulating layer 34, etching second contact holes to expose the first level interconnections and the capacitor patterns and depositing a second conductive material to form a second level interconnection 36a-d. Preferably the first level interconnection and the first conductive layer, and the second level interconnection and the second conductive layer, are made of the same material.
申请公布号 GB2341000(A) 申请公布日期 2000.03.01
申请号 GB19990011446 申请日期 1999.05.17
申请人 * SAMSUNG ELECTRONICS COMPANY LIMTED 发明人 BON-JAE * KOO;KI-NAM * KIM
分类号 H01L21/28;H01L21/02;H01L21/04;H01L21/331;H01L21/768;H01L21/8242;H01L21/8246;H01L27/10;H01L27/105;H01L27/108;H01L29/24;H01L29/732;(IPC1-7):H01L27/115 主分类号 H01L21/28
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