| 摘要 |
<p>PROBLEM TO BE SOLVED: To efficiently reduce a chip area by forming a wiring structure of a bonding pad and a semiconductor substrate at the lower part of the bonding pad formed on the surface of the semiconductor substrate. SOLUTION: Related to a chip, or a semiconductor integrated circuit device 100, a plurality of bonding pads 120 for connecting chip's outside part to its inside part are allocated along the peripheral region of the chip 100, and each bonding pad 120 is electrically connected to a core region 160 where an integrated circuit is formed through a corresponding input/output circuit 140. Related to the semiconductor integrated circuit device 100, the bonding pad 120 is arrayed in a region to be arrayed while, at the lower part of the bonding pad 120, a metal wiring or a conductive film 180 between a semiconductor substrate and the bonding pad is arrayed. Since a capacitor or a wiring structure is formed at the lower part of the bonding pad, a chip area is efficiently reduced.</p> |
