发明名称 SEMICONDUCTOR MEMORY APPARATUS
摘要 <p>PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus which can prevent incorrect writing without increasing a time required for writing. SOLUTION: The semiconductor memory apparatus has a memory cell array 101 in which nonvolatile memory cells are arranged in matrix, a data latch 102 working also as a sense amplifier, decoders 105, 103 for selecting memory cells, a write voltage generation circuit 108 for generating a higher write voltage than a source voltage which is to be fed when data is written to the selected memory cell, and an intermediate voltage generation circuit 109 for generating an intermediate voltage higher than the source voltage and lower than the intermediate voltage which is to be fed when data is written to the non-select memory cell. An output control circuit 111 is provided so that an output voltage of the intermediate voltage generation circuit 109 follows an output voltage of the write voltage generation circuit 108 before reaching a predetermined level.</p>
申请公布号 JP2000057784(A) 申请公布日期 2000.02.25
申请号 JP19980229187 申请日期 1998.08.13
申请人 TOSHIBA CORP 发明人 NAKAMURA HIROSHI;HOSONO KOJI;KANDA KAZUE;TAKEUCHI TAKESHI
分类号 G11C16/02;G11C16/04;G11C16/06;(IPC1-7):G11C16/02 主分类号 G11C16/02
代理机构 代理人
主权项
地址