| 摘要 |
PROBLEM TO BE SOLVED: To improve counting reliability of an up/down counting circuit which executes counting up and counting down by switching. SOLUTION: When the counting value of a low-order counter 21 becomes the maximum value by counting up, the counter 21 sends an activating signal S21 to a high-order counter 22 through an inverter 23 to activate. Since a clock CLK given to the counter 22 is masked by a down counting prohibiting circuit 24 and AND gates 25 and 27 in a case when counting down is designated by the change of the logical value of a signal S14 then, the counter 22 does not count down. Thus, the counter 22 does not count erroneously even though operation of stopping sending of the signal S21 and prohibiting counting of the counter 22 is delayed from the clock CLK because of gate delay and wiring delay. |
