发明名称 |
Latch up protection and yield improvement device for IC array |
摘要 |
The integrated circuits array with latch up protection includes an active array and a guard array. The active array contains a plurality of integrated circuits devices having operational functions. The guard array abutting an outer peripheral portion of the active array contains a plurality of transistors for protecting the plurality of integrated circuits devices from latch up. In general, the active array can be functional circuits like a memory array or a read only memory (ROM) array. The plurality of transistors in the guard array can be formed simultaneously with transistors in the active array and have same structure with the transistors.
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申请公布号 |
US6028341(A) |
申请公布日期 |
2000.02.22 |
申请号 |
US19980036817 |
申请日期 |
1998.03.09 |
申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
TAI, YU-CHIN;MOU, YA-NAN |
分类号 |
H01L27/02;H01L27/112;(IPC1-7):H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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