发明名称 DUAL DAMASCENE STRUCTURE
摘要 <p>PROBLEM TO BE SOLVED: To provide a dual damascene (dual etching decorative patterns) structure that is made of a material, having superior heat transfer action and accelerates semiconductor device operation. SOLUTION: This dual-damascene structure has a semiconductor substrate 210, a metal-oxide-semiconductor(MOS) transistor formed on this substrate and a metal layer. The metal layer is electrically connected to the conductive region 215 of the MOS transistor via a mutual connection part 218. Furthermore, the metal layer contains a first inter-metal region 240 and a second inter-metal region 250. The width of the first inter-metal region is about 1 to 10 times greater than that of the manufacturing line of the semiconductor device. The width of the second inter-metal layer is about 0.8 to 1.2 times greater than that of the manufacturing line. The first inter-metal region contains a dielectric 270 with a high dielectric constant to increase the heat transfer rate. The second inter-metal region contains a dielectric 280 with a low dielectric constant for shortening the resistance-capacitance delay.</p>
申请公布号 JP2000049228(A) 申请公布日期 2000.02.18
申请号 JP19980302264 申请日期 1998.10.23
申请人 UNITED MICROELECTRONICS CORP 发明人 WU JUAN-YUAN;RO KATETSU
分类号 H01L21/3205;H01L21/28;H01L21/768;H01L23/52;H01L23/522;H01L23/528;H01L29/78;(IPC1-7):H01L21/768;H01L21/320 主分类号 H01L21/3205
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