发明名称 COMMON MODE LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make variation of supply electric power smaller and to enable faster operation by providing a bias circuit, couples of input MOS transistors(TR), and plural load MOS TRs, and operating the load MOS TRs in respective triode areas by the bias circuit. SOLUTION: The bias circuit 11 includes one couple of TRs P4 and P5, which are put in a certain specific range wherein their aspect ratio is forced so that a TR P6 operates only in a triode area. Namely, when the aspect ratio of P4 is WP/LP, the aspect ratio of P5 is WP/LP/n and 1<n<4. The drain voltage VPX of P6 can be adjusted by adjusting the relation between the aspect ratios of P4 and P5 by adjusting (n). Then P6 when operating in the triode area operates like a resistance having superior linear characteristics.
申请公布号 JP2000049589(A) 申请公布日期 2000.02.18
申请号 JP19990203628 申请日期 1999.07.16
申请人 SEIKO EPSON CORP 发明人 QUANG KAICHII;PING ZUE
分类号 H03K19/086;H03K19/094;H03K19/0944;H03K19/21;(IPC1-7):H03K19/086 主分类号 H03K19/086
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