发明名称 |
Method for verifying hold time in integrated circuit design |
摘要 |
A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.
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申请公布号 |
US6023767(A) |
申请公布日期 |
2000.02.08 |
申请号 |
US19970841839 |
申请日期 |
1997.05.05 |
申请人 |
INTEL CORPORATION |
发明人 |
KUMAR, SUDARSHAN;LAN, JAMES J. C.;MANGLORE, RAJESH |
分类号 |
G06F1/10;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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