发明名称 LOW SKEW CLOCK TREE CIRCUIT USING VARIABLE THRESHOLD VOLTAGE TRANSISTOR
摘要 PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew. SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element. Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew.
申请公布号 JP2000035831(A) 申请公布日期 2000.02.02
申请号 JP19980205309 申请日期 1998.07.21
申请人 NEC CORP 发明人 MIZUNO MASAHARU
分类号 G06F1/10;H03L7/081 主分类号 G06F1/10
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