发明名称 |
METHOD FOR USING ELECTRICALLY RECONSTITUTABLE GATE ARRAY LOGIC AND DEVICE CONSTITUTED BY THE SAME |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for structuring logic constitution by using an electrically reconstitutable gate array. SOLUTION: Electrically reconstitutable gate array(ERCGA) logic chips are mutually connected through reconstitutable interconnection. The electric representation of a large-scale digital network is so converted as to adopt a hardware configuration, which operates actually and temporarily on interconnected chips. The digital network actualized on the interconnected chips is altered any time through the reconstitution connection. Consequently, a system is adapted to various purposes including simulation, prototyping, implementation and calculation. The reconstitutable interconnection is constituted by an ERCGA chip dedicated to an interconnecting function. The respective interconnected ERCGAs are not connected to all the interconnected chips, but connected to at least one pin. |
申请公布号 |
JP2000036737(A) |
申请公布日期 |
2000.02.02 |
申请号 |
JP19990132028 |
申请日期 |
1999.05.12 |
申请人 |
QUICKTURN DESIGN SYST INC |
发明人 |
BUTTS MICHAEL R;BATCHELLER JON A |
分类号 |
G01R31/28;G06F11/22;G06F11/25;G06F15/78;G06F17/50;H01L21/82;H03K19/173;H03K19/177;(IPC1-7):H03K19/173 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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