| 摘要 |
Circuit for dropping, inserting and elaborating control bytes in time division multiplexed frames, specifically SDH frames, where said control bytes are contained in overhead sequences of container sequences representing multiplexed tributary flows in said time division multiplexed frames, and where said drop, insert and elaboration circuit elaborates said control bytes to build operating statuses of the tributaries using storing means for such an elaboration. According to the present invention, said control byte drop, insert and elaboration circuit (1) comprises an arithmetical logic unit (U) operating in association with storing means comprising an external memory circuit (ERM).
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