发明名称 ERROR RATE DETECTING CIRCUIT AND RECEPTION TERMINAL EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To detect and measure the bit error of a transmission error caused by a transmission line during the operation of digital broadcasting and digital data transmission. SOLUTION: This equipment is provided with an error correcting circuit 1 for performing the error correction of a digital stream signal, corrected bit number detecting and holding circuit 2 for detecting and holding the number of corrected bits, reference bit number table circuit 3 for holding the reference number of bits to be calculated at every unit time, division circuit 4 for dividing the number of corrected bits with the reference number of bits, and output circuit 5 for outputting the divided result of the division circuit 4.
申请公布号 JP2000032365(A) 申请公布日期 2000.01.28
申请号 JP19980198484 申请日期 1998.07.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAWAMURA HIROYUKI;KAWASHIMA ICHIRO;YAMADA YUTAKA
分类号 H04N5/44;H04N5/455;H04N7/20;(IPC1-7):H04N5/455 主分类号 H04N5/44
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