发明名称 |
INTEGRATED CIRCUIT TESTER AND TESTING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To make it possible to increase the testing efficiency by simultaneously making a plurality of testings in one time contact doing no damage to terminal pads in a semiconductor integrated circuit in order to test the wafer status in the circuit wherein the pin numbers required by the testing items are notably differentiated. SOLUTION: An integrated circuit tester equipped with a prober 5 composed of a tester and a probe composed corresponding to an integrated circuit on a wafer and a transmitting means of signals between the tester and the prober 5 also a testing board 4 quick disconnectably inserted between the wafer and the prober 5 as well as a connector 41 arranged corresponding to the wafer pads on the surface of the - side of the testing board 4 simultaneously pads 42 arranged corresponding to the other side surface of the testing board 4 furthermore, the connectors 41 of the testing board 4 and the pads 42 are wired pertinent to the testing of the integrated circuit inside the testing board 4. |
申请公布号 |
JP2000031218(A) |
申请公布日期 |
2000.01.28 |
申请号 |
JP19980195544 |
申请日期 |
1998.07.10 |
申请人 |
NEC CORP |
发明人 |
AOYAMA SHINTARO;CHIKOU KENTA |
分类号 |
G01R31/26;G01R1/073;H01L21/66;(IPC1-7):H01L21/66 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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