发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To eliminate erroneous writing or reading in or from a non-selected memory cell transistor by applying specified bias to the source and the drain of the non-selected memory cell transistor connected before and after a selected memory cell transistor. SOLUTION: If a gate electrode 122 is applied with high voltage, hot electrons are generated from the tip of a channel 126 formed on the surface of a substrate 111 below a side wall 115 and part of them are trapped inside a nitride film 120. In a memory cell transistor M2 adjacent on the drain electrode 117 side to a selected memory cell transistor M3, a source region 112-4 and a drain region 113-4 are biased at the same writing potential as that at the drain electrode 117 of the selected memory cell transistor M3. Therefore, current caused to flow from the selected memory cell transistor M3 toward the non-selected memory cell transistors M2... is suppressed to the minimum and thereby erroneous wiring is prevented.</p>
申请公布号 JP2000031438(A) 申请公布日期 2000.01.28
申请号 JP19980199163 申请日期 1998.07.14
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 SATO KAZUHIKO;TATSUMI YUICHI;OTA HITOSHI;SUZUKI NORIAKI;MINAGAWA EISHIN
分类号 G11C16/02;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L27/115;H01L21/824 主分类号 G11C16/02
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