DOT CLOCK GENERATING CIRCUIT AND ITS METHOD, AND PICTURE DISPLAY DEVICE

摘要

PROBLEM TO BE SOLVED: To make stably generatable dot clock signals even in a case where the period of horizontal synchronization pulses varies in the vicinity of the interval in which vertical synchronization pulses of vertical synchronization signals are generated. SOLUTION: Two parameters are prepared to arbitrarily set the beginning and the ending of the control interval in which the period of horizontal synchronization pulses of a horizontal synchronization signal HSYNC may be changed in the vicinity of a generation interval Tv of vertical synchronization pulses. A successive counting is conducted for the number of pulses of horizontal synchronization pulses of the signal HSYNC included in the interval of one period of a vertical synchronization signal VSYNC, and a control signal PDEN having an arbitrary pulse width is generated in accordance with the number of pulses counted and the two parameters which control the beginning and the ending of the control interval. The signal PDEN controls the dot clock generating circuit which generates dot clock signals.