FAULT DETECTION IN DIGITAL SYSTEM

摘要

The present invention relates to a fault testing in digital systems and devices therefor. A processor unit (2) is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyser (3) is activated and the processor unit (2) generates a set of stimuli, influencing the appropriate logical units. The output response analyser (3) collects responses of the stimuli at different nodes (13) in the digital system (1) and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. Preferably, the present state of the processor (2) and other logical units are stored in a storage means (15) prior to the test and recovered after the testing is finished. The invention functions both at chip and board levels, and on systems with several units.