Single chip controller-memory device including feature-selectable bank I/O and architecture and methods suitable for implementing the same

摘要

A memory architecture 104 includes a plurality of arrays 200 of memory cells. Addressing circuitry 201 selects a cell of a selected one of arrays 201 for access while feature select circuitry 205 selects an access type to be performed to the selected cell. A first bus 207, 208, 209 exchanges a bit of data with the selected cell in response to the selection of a first access type. A second bus 207, 208, 209 exchanges a bit of data with the selected cell in response to the selection of a second access type.