Vertical transistor and memory cell

摘要

A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, having increased integration. This process and structure avoid the characteristic degradation caused by the leakage current associated with the trench process and structure.