发明名称 |
Method and system for determining statistically based worst-case on-chip interconnect delay and crosstalk |
摘要 |
A method and system of determining circuit performance-related characteristics, particularly delay and crosstalk, of interconnects includes defining a number of process variables which exhibit Gaussian distributions with respect to geometrical variances. A table of statistically based worst-case values representative of capacitances and resistances associated with different selections of the process variables is generated. In the preferred embodiment, the statistically based worst-case values are 3-sigma values. Also generated is a table of capacitance derivatives with respect to interconnect geometries. When a particular interconnect layout having selected process parameters is designated, the tables of 3-sigma values and derivatives are accessed to generate a resistance-capacitance (RC) net representative of the interconnect layout. The resistance and capacitance are correlated for each RC net and are partially determined by a randomized selection of values for geometries of the interconnect layout. The randomized selection of geometrical values is within the Gaussian distributions. Three-sigma delay and 3-sigma crosstalk may then be determined for the interconnect layout.
|
申请公布号 |
US6018623(A) |
申请公布日期 |
2000.01.25 |
申请号 |
US19970949048 |
申请日期 |
1997.10.10 |
申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
CHANG, NORMAN H.;KANEVSKY, VALERY;NAKAGAWA, O. SAM;OH, SOO-YOUNG |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|