SAC PROCESS USING INSULATION SPACER

摘要

PURPOSE: A SAC process using insulation spacer is provided to enhance integration by depositing an insulation spacer after conventional etching, and realize process without CB opening and CB short-cut. CONSTITUTION: The SAC process using insulation spacer comprises: a step forming a gate stack on a substrate; a step depositing a liner on the gate stack; a step depositing a BPSG layer on the liner; a step depositing a TEOS layer on the BPSG layer; a step masking a bit line contact; a step etching the bit line contact; a step striping the bit line contact; a step cleaning the bit line contact; a step etching the liner for the bit line contact; a step depositing an insulation layer on a semiconductor element after the liner etching step; and a step etching the insulation layer for forming a space for insulating the gate stack from the contact.