发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory having a redundant circuit type for selecting redundant cell arrays without adding a complicated circuit without increasing an area of a wiring region. SOLUTION: Addresses are allocated in redundant cell arrays 21 to 2m for fault remedy of a memory cell array 1. A first internal address AIN input by an address input circuit 5 is selected by a switching circuit 7 in the case of no defective address, transferred to an address decoder 3, and the array 1 is accessed. The address AIN is sent to an address converters 61 to 6m. In the case of the defective address, a second internal address BIN converted into addresses of the arrays 21 to 2m together with an identification signal S is generated. The address BIN is selected by the circuit 7, transferred to the decoder 3, and the arrays 21 to 2m are selectively driven.
申请公布号 JP2000021190(A) 申请公布日期 2000.01.21
申请号 JP19980190560 申请日期 1998.07.06
申请人 TOSHIBA CORP 发明人 HIMENO TOSHIHIKO;IWATA YOSHIHISA;IMAMIYA KENICHI;SUGIURA YOSHIHISA
分类号 G11C11/413;G11C11/401;G11C11/408;G11C29/00;G11C29/04 主分类号 G11C11/413
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