发明名称 APPARATUS AND METHOD FOR ANALYZING FAULT OF INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten a time required for an analyzing process. SOLUTION: Result data tested by a memory testing system 11 is collected by a data storage-forward-distribution machine 12, and then distributed to a plurality of distributed analyzing machines 13 (131 to 13n). The respective machines 13 analyze the data, and transmit the results to an integrated analyzing machine 14. The machine 14 integrates the analyzed data and further analyzes a fault.
申请公布号 JP2000021195(A) 申请公布日期 2000.01.21
申请号 JP19980185788 申请日期 1998.07.01
申请人 NEC CORP 发明人 TANAKA MIKIHIRO
分类号 G01R31/28;G11C29/00;G11C29/44;H01L21/66;(IPC1-7):G11C29/00 主分类号 G01R31/28
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