| 摘要 |
PROBLEM TO BE SOLVED: To prevent a latch-up by impressing an erase voltage to a memory cell well for a predetermined period, erasing the memory cell well and then discharging the erase voltage of the memory cell well by turning two signal lines in a floating state. SOLUTION: An erase voltage of a cell well is discharged while bit lines, cell source lines and all control gates of non-selection blocks not to be erased are kept in a floating state. A cell well discharge circuit CWB2 for discharging the erase voltage of the cell well after data is erased discharges the erase voltage of the cell well with a constant current, thereby preventing a potential of the cell well from decreasing suddenly. A Vcc is impressed to a gate of a transistor TD1 and a Vss is impressed to a gate of a transistor TD2. A transistor HN is controlled to be switched on by a control signal CPWELLVss2 impressed to a gate thereof after the data is erased. |
