发明名称 QUICK ACCESS CONTROL SYSTEM FOR CPU
摘要 PROBLEM TO BE SOLVED: To obtain a smooth quick access between a CPU and a quick access area by controlling the switching of a switching means for a data bus between the control means and a normal access area. SOLUTION: Data among a CPU 1 to be a control means, a quick access area 2 related to the CPU 1 and a normal access area 3 requiring a normal access related to the CPU 1 are transmitted through a data bus 4 to be an address/data line. A bus switch 5 to be a switching means for turning on/off the bus 4 is connected between the CPU 1 and the area 3. At the time of detecting an access command for urging access operation from the CPU 1 to the area 2 in accordance with a prescribed signal, a bus control part 6 controls the switching of the bus switch 5 so as to turn off the data bus 4 between the CPU 1 and the area 3.
申请公布号 JP2000020459(A) 申请公布日期 2000.01.21
申请号 JP19980187175 申请日期 1998.07.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKAJIMA IWAO;INOUE KOICHI
分类号 G06F3/00;G06F13/36;(IPC1-7):G06F13/36 主分类号 G06F3/00
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