| 摘要 |
A power on reset circuit includes: interconnected first and second inverter circuits; a capacitor connected to an input node of the first inverter circuit; and a buffer circuit responsive to voltage at an output node for generating a power on reset signal. In the power on reset circuit, in order to increase source voltage of an N channel MOS transistor in the second inverter circuit to a voltage higher than ground voltage, a diode-connected transistor is inserted between the source of the transistor and a ground node. Thus, the power on reset circuit never fails to produce the power on reset signal even when power supply voltage is dropped.
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