| 摘要 |
PURPOSE: The DRAM is for realizing fast operation by improving the read operation time in 4 bit and 8 bit page mode operation. CONSTITUTION: The DRAM comprises: a column decoder(25) which connects the corresponding bit line to a data bus line without change as to the input of a column address signal as long as page inputted later including a column address signal, being selected by address signal except the least significant n bit of the column address; a data bus line sense amp array(26) which senses, amplifies and latches data in the data bus line, with its operation being controlled by the least significant n bit signal of the column address signal; and a data output buffer(28) outputting by buffering the latched data.
|
