| 摘要 |
PURPOSE: In a flash memory cell using split gate type cells, if the reading and erase verifying operations are performed by loading the same gate voltages, a reliability of the memory is decreased because of insufficient current margin between an erased memory cell and a reference cell, wherein the insufficient current margin is originated from a voltage-current characteristic of the memory cell. CONSTITUTION: A data reading and erase verifying voltage generating circuit for flash memory cells according to the present invention, performs reading and erase verifying operations by loading different gate voltages in the reading and erase verifying operations of the flash memory cells, so that an erase margin of the memory cell is ensured sufficiently.
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