PLL CIRCUIT

摘要

An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70) to obtained sampled values. These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, an arithmetic section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).