| 摘要 |
Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer. <IMAGE> |
