发明名称 |
Multi-processor system and its network |
摘要 |
In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
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申请公布号 |
US6011791(A) |
申请公布日期 |
2000.01.04 |
申请号 |
US19960747344 |
申请日期 |
1996.11.12 |
申请人 |
HITACHI, LTD. |
发明人 |
OKADA, TETSUHIKO;HAMANAKA, NAOKI;IRIE, NAOHIKO;HAYASHI, TAKEHISA;MOCHIDA, TETSUYA;SHIBATA, MASABUMI;TANAKA, YOUICHI;ISHII, YASUHIRO |
分类号 |
G06F15/173;(IPC1-7):G06F13/38;H04L12/56 |
主分类号 |
G06F15/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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