| 摘要 |
An MPEG decoder includes a dual-speed variable length decoder (VLD) in which a code length determining portion in a feedback loop of the VLD, which loop also includes a barrel shifter and an adder-accumulator, is formed of two length tables, a high speed first length table for producing a code length determination within one clock cycle for the non-DC discrete cosine transform (DCT) coefficients and a slower speed second code length table which produces a code length determination generally in two or more clock cycles. A DCT coefficient run length decoder receives DCT coefficient codewords from the VLD consisting of level/run pairs and is configured for decoding any level/run pair in one clock cycle. By concentrating decoding speed on the variable length DCT coefficients which constitute much of the data in an MPEG data stream, sufficient decoding speed is obtained to handle MPEG-2 video as proposed for high definition television (HDTV).
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