| 摘要 |
A power-on reset circuit comprises an oscillation circuit, an oscillation end detection circuit, a voltage stabilizer for generating a predetermined voltage (VDD2) from a power-supply voltage (VDD), and a start-up circuit. The power-on reset circuit further comprises a latched circuit. While the power is rising, the latched circuit becomes of an initial state and outputs a signal for arranging the latched circuit to a power-on reset state. When a value of the VDD becomes more than the value of the VDD2, by which the VDD2 becomes of a stable state, the initial state of the latched circuit is canceled, while as the VDD becomes stable, the oscillation circuit starts the oscillation in order to arrange the latched circuit to a set state, thus outputting a signal for canceling the power-on reset state.
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