发明名称 METHOD FOR SIMULATING INTEGRATED CIRCUIT, AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To execute another simulation by reducing the influence of error generated by shape simulation using cells. SOLUTION: The number Nc of conductor areas and the number Ncell (i) of cells constituting each conductive area ci are calculated from a shape simulation result (S3), and when the number Ncell (i) in each conductive cell ci is larger than or equal to the minimum number Ncellmin of cells regarded as an electrode or a wiring, the conductive area is set up as an electrode or a wiring (S6). In the other case, a dielectric substance existing on its upper, lower, right, left, front, or rear position is substituted for the conductive area (S100). When Nc=4, Ncell (1)=16, Ncell(2)=8, Ncell(3)=1, Ncell(4)=1, and Ncellmin = 5 are set up and an upper dielectric substance is substituted for a conductive area consisting of cells less than the Ncellmin, the c1 and c2 are regarded as electrodes or wirings and a dielectric substanceε3 is substituted for the c3 and c4. After completing the processing of all conductive areas, capacity simulation e.g. can be accurately executed.
申请公布号 JPH11353338(A) 申请公布日期 1999.12.24
申请号 JP19980156084 申请日期 1998.06.04
申请人 MITSUBISHI ELECTRIC CORP 发明人 SONODA KENICHIRO
分类号 H01L29/00;G06F17/50;H01L21/00;(IPC1-7):G06F17/50 主分类号 H01L29/00
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